Digital coding scheme providing indicium at cell boundaries under prescribed circumstances to facilitate self-clocking



April 21, 1970 J. E. BISHOP 3,508,228

DIGITAL CODING SCHEME PROVIDING INDICIUM AT CELL BOUNDARIES UNDERPRESCRIBED CIRCUMSTANCES TO FACILITATE SELF-CLOCKING Filed March 28,.1967 4 Sheets-Sheet 1 5 YA/CHEU/V/Z/l 7' 0/1/ 2514 2546 mvzmon. (/dSEPH6 fi/swop f/mw/ ATTORNEY April 1, 1970 J. E. BISHOP DIGITAL CODINGSCHEME PROVIDING INDICIUM AT CELL BOUNDARIES UNDER PRESCRIBEDCIRCUMSTANCES T0 FACILITATE SELF-CLOCKING Filed March 28. 1967 4Sheets-Sheet 2 Aprll 21, 1970 J. E. BISHOP 3,503,228

DIGITAL CODING SCHEME PROVIDING INDICIUM AT CELL BOUNDARIES UNDERPRESCRIBED CIRCUMSTANCES TO FACILITATE SELF-CLOCKING Filed March 28.1967 4 Sheets-Sheet 3 QRMN 1 k L FIL K P J NR3 LSRSQ wmx wmm L F 4 l|.mKbK

NQLNLH NSSQL h fifil x351 mx i NSQL \kbsu 3mm MMQEQ bk United StatesPatent O M DIGITAL CODING SCHEME PROVIDING INDICIUM AT CELL BOUNDARIESUNDER PRESCRIBED CIRCUMSTANCES TO FACILI- TATE SELF-CLOCKING Joseph E.Bishop, Scottsdale, Ariz., assignor to General Electric Company, acorporation of New York Filed Mar. 28, 1967, Ser. No. 626,553 Int. Cl.Gllb 5/00, 5/06 US. Cl. 340-174.1 3 Claims ABSTRACT OF THE DISCLOSUREDescribed herein is a system for recording digital information onto andfor reading digital information from a storage medium by the placing ofan indicia on a storage medium at particular points within designatedareas on the storage medium. By its relative positioning within thespecific area, the indicia is representative of specified increments ofinformation.

BACKGROUND OF THE INVENTION The present invention relates generally tothe storage and retrieval of information and more particularly to thestorage of and retrieval of information in binary form.

The present information is particularly applicable, although it is notso limited, to the storage of information in digital form onto amagnetic storage medium such as those which find common usage inelectronic data processing systems.

In any storage and retrieval system, the primary objective is, ofcourse, to accurately record and retrieve the desired information. Inmodern day electronic data processing systems, however, it is becomingincreasingly important to increase the rate at which data may be broughtfrom or sent to an external storage device from the processor of thesystem which actually performs the computations and manipulations of thedata. Additionally, because of the ever increasing volume of data whichis required, it is becoming increasingly important to increase theamount of data which can be stored on a given area of storage medium.This latter feature is commonly referred to as the packing density andis normally expressed in bits per inch, that is, the number of binarybits which can be stored with respect to a given length of storagemedium.

It is known in the art that digital information can be stored on amedium having a magnetizable surface and that information thus storedmay be recovered by providing relative movement between the medium and atransducer which detects polarity changes of discrete areas of themedium surface. The detected pattern of magnetic polarization, or fluxreversals as they are commonlv called. taken in conjunction with anadditional parameter. for example, time is indicative of the informationstorcu and retrieved and this pattern is commonly referred to as a code.

Inasmuch as any given storage medium has, taken in conjunction with theequipment used to record thereon and read therefrom, a given packingdensity factor (i.e., flux transitions can only be placed so close toone another before it becomes impossible to distinguish between thetransitions) and inasmuch as these same basic conditions are prevalentwith respect to the relative speeds which can be permitted between thestorage medium and the transducer, the sole remaining manner in whichthe amount of data which can be recorded in a given length of storagemedium is limited by the pattern of flux reversals or, more simply, thecode utilized. Stated in an- 3,598,228 Patented Apr. 21, 1970 other way,the code which provides the least amount of flux reversals for a givenamount of information is that which will produce the highest amount ofinformation storage.

OBJECTS It is, therefore, an object of the present invention to providean improved data information storage and retrieval system.

Another object is to provide means for increasing the amount ofinformation which can be stored and recovered from a storage mediumwithout decreasing the distance between the flux reversals on thestorage medium.

Still another object is to provide a method and means for increasing theamount of digital information which can be placed upon a storage mediumby providing that the number of recorded indicia is less than the numberof units of information desired to be stored.

SUMMARY OF THE INVENTION Briefly stated, the present invention providesthe foregoing and other objects by providing a method and apparatus forrecording binary data in a manner such that the representation of twobinary bits is recorded within a unit of storage media or within whatwill be hereinafter referred to as a cell. This is accomplished in theillustrated embodiment of the present invention by dividing each cellinto four equal parts and by recording a flux transition or reversal atone or more of the division points within the cell in accordance with atwo binary bit combination to be recorded. The actual combination ofbinary bits represented by the fiux transition(s) indicated by therelative position of the transition(s) within the individual cell. Thepresent invention also provides, when desired and under specifiedconditions, for the insertion of a flux reversal at a particular pointwithin the cell which is not representative of data but which isutilized for synchronization purposes. This reversal may be requiredunder certain circumstances and its availability alleviates thenecessity of extremely precise equipment for the practical utilizationof applicants invention.

BRIEF DESCRIPTION OF THE DRAWING Further objects and advantages of theinvention will become apparent as the following description proceeds andfeatures of novelty which characterize the invention will be pointed outin particularity in the claims annexed to and forming a part of thisspecification. For a better understanding of the present invention,reference is made to the accompanying drawing in which:

FIG. 1 is a diagram illustrating the manner in which various binary bitconfigurations are recorded within a cell area of storage medium inaccordance with the present invention;

FIG. 2 illustrates the recording of an eight binary bit configuration infour successive storage cells;

FIG. 3 is a schematic logic diagram illustrating a preferred means forimplementing the present invention;

FIG. 4 is a timing diagram useful in the understanding of therepresentation of FIG. 3;

FIG. 5 is a chart illustrating the contents of a register shown in FIG.3 during the time in which data is being written onto the storagemedium; and,

FIG. 6 is a chart illustrating the contents of a register shown in FIG.3 during the time in which data is being read from the storage medium.

DESCRIPTION OF THE PREFERRED EMBODIMENT The manner in which informationis stored as a pattern or is coded onto a recording medium may best beseen with reference to FIG. 1. In that figure, there is shown therepresentation of a single data cell which corresponds to a specifiedarea of storage medium onto which the pattern is to be stored. It isseen that the cell is divided into four equal parts by the lines T T T Tand T collectively referred to as T times. These T times designate thesubdivisions of the data cell and it is at these times that, in the caseof a magnetic recording, the flux reversals are placed onto the storagemedium to represent the various binary bit configurations. In accordancewith the provisions of the present code, and as is illustrated in FIG.1, if a 01 binary =bit configuration is to be written, a transition orflux reversal is placed at the T time, at the M1 point of the cell. A 00bit configuration is written at T time (mid-point) while a binary bitcombination is written as a flux reversal at T point) time. The fourthpossible combination of a two bit binary designation is the 11configuration and it is seen in FIG. 1 that this is designated by a fluxreversal at both the T and T times. The remaining depiction of FIG. 1 isa reversal at T time designated synchronization reversal. Thistransition does not actually represent data in the present code but isinstead used for synchronization or clocking purposes.

As will become more apparent as this description proceeds, the presentcode adapts itself well to self-synchronization or self-clocking inreading data from the storage medium. (By self-clocking it is meant thatthe flux reversals used to designate data are also used to maintainsynchronization within the system.) It will be seen that, in certain bitconfigurations, the distance between successive flux reversals exceeds amaximum which is, essentially, established by the self-clockingcapability of the particular system. As such, in the to be describedembodiment, provision is made under these particular circumstances forinserting the flux reversal at the boundary of the cell (T time) inorder to properly maintain synchronism and to preclude the necessity ofproviding extremely stable and hence extremely expensive clocking means.There are three situations in which the synchronization reversal issupplied. These are:

01 followed by 10 01 followed by 00 00 followed by 10 These threesituations represent those binary bit configuration combinations whichwould result in a time greater than that corresponding one cell timewithout a flux revcrsal. It is to be expressly understood, however, thatthe synchronization reversal does not form a portion of the recordeddata. It should also be mentioned at this time, and as will be morefully explained hereinafter, that in the strictest sense of the word theflux reversal which occurs at T time and which represents the binary bitconfiguration 00 is also unnecessary. It is, however, utilized in thepresent implementation in order that if, for example, a long series ofzeros were to be written there would be some flux reversals to maintainsynchronism within the system Referencing now FIG. 2, there is shown thereversal pattern which would be written onto a magnetic recordingsurface for the eight binary bit configuration shown which is, readingleft to right, 10 01 O0 11. These eight binary bits are respectivelyallocated one to each of four cells 1 through 4. As is shown in FIG. 2the 10 binary bit configuration is recorded as a reversal at T time ofcell 1 and the 01 binary bit configuration is recorded as a fluxreversal at T time of cell 2. The 00 binary bit configuration is writtenat T time of cell 3 while the 11 bit configuration is written as fluxreversals at both T and T time of cell 4.

It will be remembered that previous mention was made of asynchronization reversal. This is illustrated at the boundary (T time)between cell 2 and cell 3. It may be seen from FIG. 2 that were thisreversal not present there would exist five T times or cell subdivisionsbetween reversals in recording the four bit combination ()1 00. Inasmuchas this would, in the normal system, represent too great a time tomaintain proper synchronization, the synchronization reversal isinserted at the common cell boundary. It is noted that this combinationof 01 00 is one of the three situations set forth above.

For a more complete understanding of the invention, reference is made tothe logic schematic of FIG. 3 and its accompanying timing diagram, FIG.4. Before beginning the explanation of these figures, however, it isbelieved beneficial to briefly explain the terminology to be used. Thesignals to be described will be referred to as high level or binary lsignals and low level or binary 0 signals. The logic illustrated is ofconventional nature. That is, an AND-gate is a logic element whichprovides at its output a high level or binary 1 signal when each of itsinputs is a binary 1. An OR-gate is a multiple input logic element whichprovides a binary 1 or high level output when one or more of its inputsis a binary 1. The small circle which is present at the input side ofseveral of the depicted elements of FIG. 3 indicates the inversionfeature. By inversion is meant simply that a binary 1 signal appliedthereto appears as a binary 0 signal to the element and conversely abinary 0 signal appears as a binary 1 signal to the element. The termflip-flop as is used in the present description designates a bistablemultivibrator with its two stable states being a set state in whichthere is a binary 1 at its 1 output terminal and a reset state in whichthere is a binary 0 at its 1 output terminal. Two types of flip-flopsare utilized in the present description. The first type of flip-flop hastwo input terminals, an S (set) terminal, and an R (reset) terminal. Inthis device, a binary 1 applied to the S terminal will place theflipflop into its set state and a binary I placed at its R terminal willplace the flip-flop into its reset state. The other type of flip-flopdiffers from that just described only with respect to the inclusion of athird input terminal designated T. Flip-flops thus designated aretrigger flip-flops and their operation differs from that previouslydescribed in that the flip-flop will change its state only upon theapplication of a binary 1 at the T terminal simultaneously with a binaryl to either of the S or R input terminals.

TIMING Specifically referencing now FIG. 3 and its associated timingdiagram, FIG. 4, there is shown a storage medium 10 which in theillustrated embodiment is in the form of a disc having a magnetizablecoating. The disc is mounted for rotation by a suitable means, notshown, in the counterclockwise direction about a central axis 12. On thedisc are a timing track 14 and a data track 16 which are operative tostore intelligence in the form of discrete magnetically polarized areas.Associated with the timing track 14 is a suitable transducer 18 whichserves to generate electrical signals in response to the motion of thedisc 10 and the changing polarity of the discrete areas. The signalsthus generated are amplified by an amplifier 20 and applied as one inputto an OR- gate 22. Similarly, a transducer 24 associated with the datatrack 16 provides suitable electrical signals which are amplified bymeans of an amplifier 26, the output of which is also applied to theOR-gate 22. OR-gate 22, although it is illustrated as a simple OR-gate,will in reality perform a somewhat more complex function, namely that ofselectively gating either the signals from the timing track or from thedata track, or from both tracks to a pulse shaper 28. However, inasmuchas this function does not forma part of the present invention, it isbelieved suflicient for the present description to illustrate thisoperation purely as an OR function.

The output of the pulse shaper 28 which, as its name implies, modifiesthe signals from the OR-gate 22 to a more desirable square wave shape,is amplified by means of an amplifier 30 whose output is applied to aphase detector 32. The output of the phase detector 32, whose functionwill be described shortly hereinafter, is supplied to a voltagecontrolled oscillator 34, the output of which is a signal designatedQVFO. The QVFO signal is a square wave signal having a frequency, in thepresent example, of four times the repetition rate of data celloccurrence (see FIG. 4). The output of the voltage controlled oscillator34 is supplied via a feedback loop to the phase detector 32. The purposeof the phase detector 32 is to compare the frequency of its input fromthe amplifier with that from the voltage controlled oscillator 34 and toprovide a voltage signal, either positive or negative, representative ofthe difference in phase between these two signals. This voltage to thevoltage controlled oscillator 34 causes the oscillator 34 to vary itsoutput frequency such that the output signal QVFO is in synchronism withthe basic frequency of the signals being derived from either the timingor data tracks of the disc 10.

The QVFO signal from the oscillator 34 is applied as an input to afrequency divider 36 whose output is a signal designated QBCK which, asmay be seen in FIG. 4, is a positive going pulse which occurs at onehalfthe frequency of the QVFO signal. The QBCK Signal from the frequencydivider 36 is applied, inter alia, to the first stage of a three stagecounter designated hit counter 38. The hit counter 38, which may be ofconventional design, furnishes three outputs. The first output from thehit counter 38 is a signal FBCO (FIG. 4) which is a square wave signalhaving a frequency onequarter of that of the QVFO signal. Furtherexamination of the FBCO signal as shown in FIG. 4 shows that the FBCOsignal is designated at various portions by the designations DBClthrough DBC6. The other two signals 'which are shown derived from thehit counter 38 and are two signals designated bit count=1 and bitcount=6, respectively corresponding to the DBCl and DBC6 portions of theFBCO signal. By way of explanation of the bit counter 38, it was statedthat this is a three stage counter and as such in the binary systemwould normally possess the capability of providing eight distinctcounts. However, in the presently being described example, the size ofthe data character being utilized is a six bit character and thereforethe hit counter, along with other components of the system, is designedto accommodate a six binary bit character. As such, the bit counter 38counts up through six and then resets to the count of one.

The QVFO signal is also supplied to a pulse shaper 40 the output ofwhich is designated as QFUL which, as may be seen in FIG. 4, is a trainof narrow positive going pulses occurring at the frequency of the QVFOsignal. The QFUL signal is supplied as an input to a two stage counter44 which is essentially two flip-flops in a counter configurationdesigned to step through the binary designations of 0 through 3. The oneoutput of the first stage of the counter 44 is a signal designated FCTSwhich, as may be seen in FIG. 4, is a square wave signal of one-half thefrequency of QFUL. The four output terminals of the two stage counter 44are applied as inputs to four AND-gates 45 through 48 in a manner suchthat the outputs of these four AND-gates, DCTO, DCTI, DCTZ, and DCT3(FIG. 4), divide the cell times into four equal parts. The signals thusfar described provide the necessary timing for the Writing ofinformation onto or reading the information from the storage medium, inthe present example the disc 10.

WRITE OPERATION In the operation of the write cycle of the presentinvention, information is brought into the system of the presentinvention to a sequencer and data supply unit 50 via an information bus52. This information enters the unit 50 prior to the beginning of awrite cycle and contains a six binary bit character and a designationthat is to be a write operation (a write command). This informationwould normally come from another component within the total of the dataprocessing system, for example, the data processor. In response to theinformation brought in via bus 52, the unit 50 supplies the six bit datacharacter via a bus 54 to a six bit A- Register 56 which acts as atemporary holding register. Because this is to be a write operation, theunit 50 supplies three additional signals, a write signal which issupplied to a three input AND-gate 58, a signal designated FSBR whichindicates that a shift to the B-Register is necessary (also serving asone input to the AND-gate 58), and a signal QXAB. The QXAB signaleffects the transferring of the contents of the A-Register 56 to aB-Register 64. The other input to the AND-gate 58 is the inversion ofthe DBC6 signal. The output of the AND- gate 58 forms one input to anOR-gate 60 which in turn serves as one of two inputs to an AND-gate 62.The other input to the AND-gate 62 is the QBCK signal. The output ofAND-gate 62, QSBR, is applied to the T terminal of the first stage (B ofthe B-Register 64.

The B-Register 64 is a six bit register comprised of six flip-flopsdesignated respectively, reading right to left, B through B B-Register64 is the main data register of the system and is a register into whichdata is shifted serially during the read operation and from which datais shifted serially during the write operation.

Continuing now with the description of the writing operation, the sixbinary data bits in the A-Register 56 are transferred in parallel to theB-Register 64 via lines 55 with the occurrence of that QSBR signal fromAND-gate 62 effected by the QBCK pulse designated count 1 in FIG. 4. Atthe same time, the previous content of the B flip-flop of the B-Registeris transferred to an FWDl flip-flop 66. Flip-fiop 66 is a triggerflip-flop and its T terminal is connected to the output of an AND-gate68 whose two inputs are the QBCK and the inversion of FBCO. Thus it isseen that each time FBCO is at the low level and there occurs a QBCKsignal, AND-gate 68 is enabled thus enabling flip-flop 66. Also at thissame time, the content of another flip-flop 70 (FBRP) is transferred toan FWDt) flip-flop 72. The flip-flops 7t) and 72 are each triggeredflip-flops with the T terminal of FBRP being connected to the QSBRsignal and the T terminal FWDO connected to the output of the AND-gate68. At the time of this transfer FBRP 70 contained the last binary bitof the character immediately preceding the one which is presently to bewritten.

FIGURE 5 illustrates the contents of the B-Register as well as theflip-flops FBRP, FWDt) and FWD1 during this and each of the succeedingperiods of time. Referencing that figure it is seen that at count 1 ofthe QBCK signal there occurs a parallel shift of the data in the A-Register to the B-Register to provide the contents therein. (In furtherexplanation of FIG. 5, and additionally FIG. 6 which is to be utilizedin the description of the reading operation, the left-hand columnspecifies that actual flip-flop involved while the several additionalcolumns indicate the contents of the actual flip-flop with respect tothe original contents of the B-Register or in the case of FIG. 6, thefinal contents of the B-Register. The 1s and Os within the parenthesesspecify the binary value contained in accordance with the specificexample being utilized for purposes of explanation. For example,referencing FIG. 5, at DBC3 time of FBCO the B flip-flop will containthe original contents of the B flip-flop, in the present example, abinary 0.)

Carrying through with the first six binary bits of the example initiatedwith respect to FIG. 2, that of writing a 10 01 00, it is seen (FIG. 5)that at this time the flipflops B B B and B will contain binary Os whileflipflops B and B will contain binary ls. The state of the FBRPflip-flop is at this time immaterial while the FWDO' and FWDl flip-flopscontain respectively the original B and B designations of the characterpreceding the one now to be recorded. Upon the assumption that the FWDOand FDWl flip-flops 72 and 66 each contain binary Os, the last binarydigits of the preceding character, it is seen that during the occurrenceof DCT1 a three input AND- gate 74 will be enabled, inasmuch as the 1outputs of the two flip-flops 66 and 72 are s, to thus provide a signalto a two input OR-gate 76 the output of which is designated DD13. TheDD13 signal forms one input to each of two 2 input OR-gates 78 and 94.The outputs of these two OR-gates form respectively an input to each oftwo AND-gates 80 and 96. AND-gates 80 and 96 each additionally includean input which is the QFUL signal and also the one and zero outputs,respectively, of a FWDC flip-flop 82. Thus it is seen that each time theDD13 signal is a binary 1 the FWDC flip-flop 82 will, upon theconcurrence of the QFUL signal, be caused to change its state or totoggle.

The output of the FWDC flip-flop 82 is supplied to a two input AND-gate84, the other input of which is the write signal from the sequencer anddata supply unit 50. With the enabling of this gate a signal is providedwhich is supplied to an amplifier 86, the output of which is supplied tothe transducer 24 to thereby write a flux transition on the data track16 of the disc 10. This transition is written at the center of a datacell and represents the binary bit configuration ()0.

Also at this same time, count 2 of the QBCK signal (FIG. 4), theAND-gate 62 was enabled to provide the QSBR signal which was supplied tothe B-Register 64 to serially shift that register to the right such thatthe original content of B is supplied to the FBRP flip-flop 70 and theoriginal content of B is now located in B Similarly, each of the otherportions of the B-Register has been shifted to the right by one, suchthat at this time the contents of the B-Register and the FBRP, FWDO andFWD1 flip-flops are as is illustrated in the DBC2 column of FIG. 5. (Theprime designation in this figure indicates the original contents of Band B of the word immediately preceding the word being written.)

Continuing with the example, at this time the FWDO flip-flop 72 and theFWD1 flip-flop 76 contain binary Os to designate the last two digits ofthe previous character while the B portion of the B-Register and theFBRP flipfiop 70 contain a combination, the first two digits of the newcharacter. This, it will be remembered from the preceding description,is one of the combinations which in the present system requires thewriting of a synchronization bit. Referencing again FIG. 3, it is seenthat the 1 output terminal of B forms one input of a two input AND-gate84 the other input of which is the inversion of the 1 output of the FWDOflip-flop 72. Inasmuch as B and FWDO contain a binary 1 and a binary 0respectively, the output of the AND-gate 84 will be a binary 1. Theoutput of AND gate 84 is applied to an OR-gate 86 the output of whichforms one input to a four input OR-gate 88. A second input to AND-gate88 is the inversion of the 1 output terminal signal of FWD1 flip-flop 66and, inasmuch as this'flip-flop has been previously stated to contain abinary 0, this is eifectivelya binary 1 supplied to AND- gate 88. Thethird input to AND-gate 88 is from the 1 output terminal of the FBRPflip-flop 70 which, as has been stated, now contains the originalcontents of the B portion of the B-Register 64 and is a binary 0. Thisinput to AND-gate 88 when inverted as indicated appears as a binary 1.The fourth input to AND-gate 88 is the WCT3 signal. Thus, at theoccurrence of this latter signal AND- gate 88 will be enabled to providean output to OR-gate 76 which in turn provides the DD13 signal which, aswas previously discussed, will upon the occurrence of the QFUL signaloccurring at the end of the DCT3 time, toggle the FWDC flip-flop 82 toagain write a flux reversal onto the data track of the disc 10. Thisreversal will occur at a boundary of a cell, as is illustrated in FIG.4, and is a flux reversal to be utilized for synchronization purposesand not as data.

At the occurrence of the QBCK signal designated count 3 in FIG. 4, theQSBR signal is again generated to serially shift the B-register and tovary the contents of the FBRP,

FWDO, and FWD1 registers 70, 72 and 66 respectively. With this transferthe content of the several flip-flops is as indicated in the DBC3 columnof FIG. 5. More specifically, with respect to the pertinent registersfor writing, it is seen that the FWD1 flip-flop contains the originalcontent of the B (a binary 1 in the present example) and the FWDOflip-flop contains the original content of B (binary O). The FBRPflip-flop contains the original content of B (a binary 1) and B containsthe original content of the B portion of the B-Register (a binary 1). Itis noted that the FWDO and FWD1 flip-flops 72 and 66 now containrespectively a binary 0 and a binary 1, the first two bits of the newcharacter to be written. This in the present example is a 10 bitconfiguration which will be written during DBC4 time at the occurrenceof the DCT2 signal. This may be seen in FIG. 3 in that inasmuch as theFWD1 flip-flop 66 contains a binary 1 in its 1 output terminal is highand forms one input to a two input AND- gate 90, the other input ofwhich is the DCT2 signal. The output of the AND-gate 90 is supplied asone input to an OR-gate 92 whose output is designated DD02. The DD02signal forms one input to each of the two OR-gates 78 and 94 whoseoutputs effect, as has been previously explained, the changing of stateor toggling of the FWDC flip-flop 82. With the toggling of the FWDCflip-flop 82 there is written via gate 84, amplifier 8'6 and transducer24 a flux transition onto the data track 16, a transition correspondingto the end of DCT2, or, as is shown in FIG. 4, at point within cell 2.

At that QBCK signal designated as count 4 (FIG. 4), the B-Register isagain serially shifted and the content of B as it existed prior to theshift is transferred to FBRP (QSBR is also present) and the content of Bas it existed prior to the shift is transferred to B However, inasmuchas at this time the PBCO signal is at a high level, AND- gate 68 is notenabled and the contents of FWD1 flipflop 66 and FWD1) flip-flop 72 arenot changed. The contents of the several flip-flops as they exist atthis time are illustrated in that column of FIG. 5 listed under the DBC4time. With respect to the binary configuration of the present example,FWD1 contains a binary 1, FWDO a binary 0, FBRP a binary 1, and B abinary 0.

With the occurrence of that QBCK signal designated count 5, the QSBRsignal is again generated to serially shift the B-Register 64 and,because the FBCO signal is now a low level signal, the output ofAND-gate 68 is a binary 1, as is the' QSBR signal, to thereby allow themodification of the FBRP, FWDO and FWD1 flipflops. The B- Register andthe latter three flip-flops now contain that illustrated in FIG. 5,column DBCS. Insofar as their binary content is concerned, it is seenthat B B FBRP and FWD1 all contain binary 0s and FWDO contains abinary 1. The FWDO and FWD1 flip-flops 72 and 66 respectively nowcontain the next two bit configuration 01 which is to be written.Inasmuch as the 1 output of the FWDO flip-flop 72 is a high level andAND-gate 95 will be enabled with the occurrence of the DCTO signal. Theoutput of AND-gate 95 is supplied to the OR-gate 92 to form the DD02signal which is effective to toggle, at the QFUL pulse occurring at theend of the DCTO pulse during DBCS time, the FWDC flip-flop 82. As beforethe changing of state of the flip-flop 82 causes a flux transition to berecorded onto the data track 16. Thus, the second two bits of the sixbit character which is desired to be written has been accomplished.

With the occurrence now of the QBCK pulse designated count 6, the QSBRsignal will again be generated to serially shift the B-Register but onceagain because of the level of the FBCO signal, the contents of the FWDOand FWD1 flip-flops 72 and 66 are not changed.

Referencing FIG. 5, column DBC6, it is seen that a 01 combination existsin the FWD1 and FWD!) flip-flops and a 00 combination is present in theB and FBRP flip-flops. This is a second of the specified combinationswhich require the writing of a synchronization flux reversal. A binary 1is now being maintained in the FDWO flip-flop 72 and a binary is beingmaintained in the FWDl flip-flop 66. Binary US are being maintained in Band the FBRP flip-flop 70. This situation will, with the occurrence ofthe DCT3 signal, enable AND-gate -88 to thus enable OR- gate 76 theoutput of which is the DD13 signal. At the occurrence of the QFUL signalat the end of the DCT3 signal the FWDC flip-flop 82 will again changestate to thus write a synchronization flux reversal at the cell boundaryon the data track 16.

At the same time this synchronization flux reversal is Written, thesecond count 1 shown in FIG. 4, the last two bit binary configuration(00) of the character being written, is parallel shifted at theoccurrence of the QBCK signal into the FWDO flip-flop 72 and the FWDlflip-flop 66. The present contents of flip-flops are shown in FIG. underthat column designated DBC1. Once again, as was previously explained,with binary 0s in FWDO and FWDl flip-flops, AND-gate 74 is enabled withthe occurrence of the DCTl signal to generate the DD13 signal and togglethe FWDC flip-flop 82 with the occurrence of that QFUL signal appearingat the end of DCTZ time.

Also at the second count 1, a new six bit character which was brought invia bus 52 to the sequence and data supply unit 50 and placed into theA-Register 56 at a time prior thereto, is parallel shifted from theA-Register 56 to the B-Register 64 in the manner previously described.

The only bit configuration which is possible with two binary bits andwhich was not considered in our previous example is the 11 combination.Very briefly, it is seen that if this combination exists in the FWDO andFWDl flip-fio-ps, AND-gate 95 will be enabled to provide a DD02 signalto toggle the FWDC flip-flop 82 when the QFUI signal occurs at the endof DCTO time. AND-gate 00 will be enabled to provide the DD02 signalfrom OR-gate 92 to toggle the FWDC flip-flop 82 when the QFUL signaloccurs at the end of DCT2 time. Thus, two flux reversals, one at the Mtand one at the ll points of the cell period will be written for an 11.While only two of the three examples of providing the synchronizationflux reversal for various bit combinations of characters have beenexplained, it is readily ascertainable from FIG. 3 a 01 bitconfiguration followed by a bit configuration will result in the writingof a synchronization reversal.

While the foregoing description of the write operation has beenexplained with respect to timing initially derived from a timing trackon the storage medium, in this case a disc, it is to be expresslyunderstood that this is an expediency inasmuch as such a track isnormally available on a data recording disc. It is not, however, arequirement, of the present invention. If desired, the output of aprecision oscillator could be utilized to initiate the generation of theseveral timing pulses and timing marks.

READ OPERATION The timing signals in the read operation of the presentinvention are generated in the manner previously described with theexception that, inasmuch as this is a selfclocking system, the signalswhich initiate the various timing signals are derived from the datatrack itself through amplifier 26. The use of data signals as opposed tothe timing track as was previously described is a function of theOR-gate 22 as was heretofore explained. It should also be explained,before proceeding with the read operation, that because of the logicused in the present illustration the data cell divisions do not fallexactly as is indicated in FIG. 4 which are those for the writeoperation. Instead, with respect to the DCT times, the data celldivisions are displaced to the left by one time. That is, a 00 bitcombination occurs during DCTO and a 10 bit combination is read duringDCTl. Similarly, a synchronization reversal occurs during DCT2 time anda 01 bit combination is read during DCT3 time.

With the initiation of a read operation, a read command is brought invia bus 52 to the sequencer and data supply unit 50 which, in responsethereto, generates two signals, the FSBR signal and a read signal. Thesetwo signals form the two inputs to an AND-gate the output of which formsone input of the OR-gate 60. As before, the output of OR-gate 60 allowsAND-gate 62 to be enabled with each occurrence of the QBCK signal togenerate the QSBR signal. The read and QBCK signals also form two inputsof a three input AND-gate 102 the output of which is designated QXBA.This signal effects the parallel transfer of the B-Register to theA-Register via lines 55. The third input to the AND-gate 102 is from the1 output terminal of a BFUL flip-flop 104. The BFUL flip-flop 104 isplaced into its set state by the QBCK signal at the end of the signal,bit count=6, from the bit counter 38. The bit count=6 signal correspondsto the DBC6 period of the FBCO signal (FIG. 4). Flip-flop 104 is placedinto a reset state :by the QBCK signal at the end of the bit count=1signal from the bit counter 38. The bit count=l signal corresponds tothe DBCI time of the FBCO signal of FIG. 4. Inasmuch as the BFULflip-flop 104 is a trigger flip-flop having the QBCK signal applied toits trigger terminal, it can only change its state with the concurrenceof one of the two above specified signals and the QBCK signal.

Electrical signals indicative of the data recorded on the data track 16of the disc 10 are supplied from the pulse shaper 28 through a suitabledelay means 106 to form one input to each of two AND-gates 108 and 110.These signals are also delivered to the sequencer and data supply unit50 for purposes of synchronizing that unit. Data from the output of thedelay means 106 is designated QONE and will appear as a positive goingpulse with each flux reversal which was recorded on the data track 16.The second input to the AND-gate 108 is the DCT3 signal such that uponthe concurrence of the DCT3 signal and a pulse on QONE, AND-gate 108 isenabled to place an FRDO flip-flop 112 into its set state. The FRDOflip-flop is placed into its reset state by the logical conjunctivecombination of the signals DCTl and QBCK. The second input to theAND-gate is the signal DCT 1. Upon the concurrence of this signal with apositive pulse QONE, AND-gate 110 will be enabled to place into its setstate an FlQDl flip-flop 114. The FRDl flip-flop 114 is placed into itsreset state by the application to its reset terminal of the conjunctivecombination of the DCT3 signal with the QBCK signal.

The 1 output terminal of the FRDO flip-flop 112 is connected to oneinput of an AND-gate 116 whose output forms one input of an OR-gate 118the output of which is a signal DRDB. The second input to AND-gate 116is the signal FBCO such that the output of AND- gate 116 is at a highlevel when the FRDO flip-flop 112 is in its set state and the FBCOsignal is a high level. The 1 output terminal of the FRDI flip-flop 114forms one input to a two input AND-gate 120, the other input of WhlCh isthe inversion of the FBCO signal such that the output of AND-gate 120 isa binary 1 when the FRDI flip-flop is set and the FBCO signal is at alow level. The output of AND-gate 120 forms the second input to OR- gate118 which, as was previously stated, is the DRDB signal. The DRDB signalis applied to the set terminal of the B flip-flop of the B-Register andits inversion is connected to the reset terminal of that same flip-flop.Thus, when DRDB is a high level signal, and with the occurrence of theQSBR signal, the B flip-flop of the B-Register will be set or willcontain a binary 1. Conversely, when the DRDB signal is at a low leveland the QSBR pulse occurs, the B flip-flop of the B-Register will beplaced lnto its reset state, i.e., containing a binary 0.

The read operation is substantially as follows and will be explainedwith respect to the character previously recorded which was a 10 01 00binary configuration. Referencing once again FIGS. 3 and 4, at theoccurrence of the QBCK signal designated count 1, the BFUL flipflop 104is set (the bit count=6 signal being a binary 1 at that time). Also atthe count 1 signal, the last bit of the previous character was shiftedinto B of the B-Register from the DRDB line with the occurrence of QSBR.This, as will be remembered, was a binary and therefore the signal DRDBwas a low level signal.

The first positive pulse on QONE occurs, as may be seen in FIG. 4,during DCTl time. The combination of these two signals enables AND-gate110 to place the FRDI flip-flop 114 into its set state. During this timeneither of the AND-gates 116 nor 120 is enabled such that the DRDBsignal is at a low level. With the appearance of the count 2 QBCKsignal, several events occur. Because the BFUL flip-flop 104 is in theset state at this time, the QXBA signal is generated to transfer thecontents of the B-Register 64 to the A-Register 56. The BFUL flip-flopis not reset. Also with the occurrence of the count 2 signal, the QSBRsignal is generated and the binary 0 of the DRDB signal is stored into Bof the B-Register 64. During the DBC2 when the signal PBCO becomes abinary 0 and with FRDl still set, AND-gate 120 is enabled thus causingthe DRDB signal to become a binary 1.

The next QONE pulse occurs during DCT3 time thus enabling AND-gate 108and placing the FRDO flip-flop 112 into its set state. At this time,however, AND-gate 116 is disabled because of the low value of the FBCOsignal. At the count 3 QBCK signal, the B-Register is serially shiftedtransferring the contents of B into B Because the FBCO signal is now abinary 1. AND-gate 116 is enabled resulting in a high level DRDB signalat the set terminal of the B flip-flop to place' a binary 1 in position5 of the B-Register 64. The B-Register contents are now as shown in theDBC3 column of FIG. 6. Referencing that figure, it is seen that Bcontains a binary 1 and B contains a binary 0. (These, respectively,will be the final B and B bits of the B-Register when the full characterhas been shifted in.) Also with the occurrence of the count 3 QBCKsignal which occurs at the end of DCT3 time, the FRDl flip-flop 114 isreset.

During DBCS time the FRDl) flip-flop 112 is set and the signal FBCO isat a high level. Thus, DRDB is a high level signal. At the count 4 QBCKsignal, the 13- Register is againn shifting and the high level signalwhich is present on the DRDB is recorded or placed as a binary 1 into Bof the B-Register 64. The contents of the B- Register are now as shownin the DBC4 column of FIG. 6. Also with the occurrence of the count 4QBCK and the DCTl signals the FRDO' flip-flop 112 is reset. The nextpulse occurring on QONE is during DCT2 time of DEC-4 time. This pulsecan set neither the FRDO nor the FRDl flip-flops and it is, therefore,ineffective as a data transfer. It will be remembered that this was thetransition which was recorded solely for purposes of synchronizationmaintenance and not at data.

At the occurrence of the count 5 QBCK signal, neither of the flip-flops112 nor 114 is set and the DRDB signal is at a low level. Therefore,with the generation of the QSBR pulse the contents of the B-Register areshifted to the right and the low level DRDB signal places the Bflip-flop of the B-Register into its reset state. At this point in timethe B-Register contains what will be ultimately bits 0 to 3 in the B toB flip-flops of the B-Register 64 (see column DBC5 of FIG. 6).

The next QONE pulse occurs in the period of the DCTO signal during DBC5time. Inasmuch as a pulse occurring during DCTO time cannot set eitherof the flip-flops 112 or 114, the line DRDB is at a low level such thatwith the occurrence of the count 6 QBCK pulse the B-Register 64 isshifted to the right and the low level signal on DRDB (a binary O) isplaced into the B flip-flop of the B-Register 64. Again referencing FIG.6, the present status of the B-Register is indicated in the DBC6 column.

With the occurrence of the second count 1 QBCK pulse, and with thepresence of the bit count=6 signal applied to the set terminal of theBFUL flip-flop 164, that flip-flop is placed into its set state. Alsowith the occurrence of the count 1 pulse the B-Register is again shiftedto the right and the DRDB line being at a low level places a binary 0into the B flip-flop. The B-Register now contains a full six bitcharacter and its contents are as indicated in the DBCl' column of FIG.6. By the comparison of this to the DBCl column of FIG. 5, it is seenthat this is the identical character that was written onto the storagemedium during the description of the Write cycle.

At the time of the next count 2 pulse of QBCK the QXBA signal is againgenerated and the contents of the B-Register are transferred in parallelto the A-Register and hence to the sequence and data supply unit forsubsequent utilization. Also at this time the first bit of the nextcharacter would be shifted into the B-Register as was previouslyexplained.

From the foregoing explanation of the read operation it is seen thatonly those pulses which occur during the times DCTl and DCT3 areeffective to set either the FRDO flip-flop 112 or the FRDI flip-flop114. From this the conclusion can be drawn that those flux reversalswhich were written onto the data track for purposes of synchronizationand those which represent the 00 bit configuration are actuallysuperfluous to the read operation except insofar as they are necessaryto maintain synchronization of the timing system.

From the foregoing it is seen that there has been shown and described ameans and method for recording binary data in a manner which allows agreater amount of data to be recorded with a relative few number ofpulses. It should be explained that while the transition and 00 pulsesare not necessary to the reading operation, they are not harmful indecreasing the time between fiux reversals in that their occurrence doesnot reduce the minimum spacing between reversals in recording withoutthese pulses.

While the principles of the invention have now been made clear in anillustrative embodiment, there will be immediately obvious to thoseskilled in the art many modifications of the structure, arrangement,proportions, the elements, materials, and components, used in thepractice of the invention, and otherwise, which are particularly adaptedfor a specific environment and operating requirements without departingfrom these principles. The appended claims are therefore intended tocover and embrace any such modifications, within the limits only of thetrue spirit and scope of the invention.

What is claimed is:

1. An information storage and retrieval system comprising a magneticstorage medium capable of assuming and maintaining magneticallypolarized regions within localized areas of said medium; transducermeans responsive to a waveform of electrical signals for recording aseries of polarization changes on said medium within sequentiallyoccuring time intervals; means for associating a two binary bitconfiguration with each of said time intervals; and means for generatingsaid waveform including first means for producing a first electricalsignal at a first point in time Within one of said time intervals inresponse to a first two binary bit configuration, second means forproducing a second electrical signal at a second point in time withinone of said time intervals in response to a second two binary bitconfiguration, said first and second means producing said first and saidsecond signals at said first and second points in time within one ofsaid time intervals in response to a third two binary bit configurationand third means for producing a third electrical signal at a third pointin time within one of said time intervals in response to a fourth twobinary bit configuration.

2. An information storage and retrieval system comprising a magneticstorage medium capable of assuming and maintaining magneticallypolarized regions within localized areas of said medium; transducermeans responsive to a waveform of electrical signals for recording aseries of polarization changes on said medium within sequentiallyoccurring time intervals; means for associating a two binary bitconfiguration with each of said time intervals; and means for generatingsaid wave form including first means for producing a first electricalsignal at a first point in time Within one of said time intervals inresponse to a binary bit configuration of 01, second means for producinga second electrical signal at a second point in time within one of saidtime intervals in response to a binary bit configuration of 10, saidfirst and second means producing said first and said second signals atsaid first and second points in time with one of said time intervals inresponse to a binary bit configuration of 11, and third means forproducing a third electrical signal at a third point in time within oneof 14 said time intervals in response to a binary bit configuration of00.

3. An information storage and retrieval system in accordance with claim2 which further includes additional means responsive to two successivetwo binary bit configurations for producing a fourth electrical signalat a fourth point in time within one of said time intervals in responseto predetermined combinations of two successive two binary bitconfigurations.

References Cited UNITED STATES PATENTS 3,374,475 3/1968 Gab'or 340-174.1

BERNARD KONICK, Primary Examiner W. F. WHITE, Assistant Examiner U.S.Cl. X.R. 34674

